Inverter including transistors having different threshold voltages and memory cell including the same

ABSTRACT

Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2021-0168696 filed on Nov. 30, 2021, and KoreanPatent Application No. 10-2022-0134349 filed on Oct. 18, 2022, in theKorean Intellectual Property Office, the disclosures of each of whichare incorporated by reference herein in their entireties.

BACKGROUND

Embodiments of the present disclosure described herein relate to aninverter, and more particularly, relate to an inverter includingtransistors having different threshold voltages and a memory cellincluding the same.

A multi-valued logic (MVL) system may be a solution to overcome adimensional down-scaling issue in a conventional binary logic system.The multi-valued logic system may implement a functional block by usinga logic gate. Because the multi-valued logic system has a higherimplementation order of logic gates compared to the binary logic system,a silicon area of a routing wire may be reduced and power consumptionmay be reduced. For the completeness of a ternary digital system such asa ternary microprocessor, the implementation of a storage component suchas a ternary static random access memory is highly recommended.

SUMMARY

Embodiments of the present disclosure provide an inverter includingtransistors having different threshold voltages and a memory cellincluding the same.

According to an embodiment, an inverter includes a first P-MOStransistor that is connected between a node receiving a drain voltageand a first path node and operates based on an input voltage, a firstN-MOS transistor that is connected between the first path node and anoutput terminal outputting an output voltage and operates based on thedrain voltage, a second P-MOS transistor that is connected between theoutput terminal and a second path node and operates based on a groundvoltage, a second N-MOS transistor that is connected between the secondpath node and a node receiving the ground voltage and operates based onthe input voltage, a third P-MOS transistor that is connected betweenthe first path node and the second path node and operates based on theinput voltage, and a third N-MOS transistor that is connected betweenthe first path node and the second path node and operates based on theinput voltage. The first P-MOS transistor has a first threshold voltage,each of the second P-MOS transistor and the third P-MOS transistor has asecond threshold voltage higher than the first threshold voltage, thesecond N-MOS transistor has a third threshold voltage, and each of thefirst N-MOS transistor and the third N-MOS transistor has a fourththreshold voltage higher than the third threshold voltage.

According to an embodiment, a memory cell includes a first inverter thatincludes an input terminal connected with a first storage node and anoutput terminal connected with a second storage node, a second inverterthat includes an output terminal connected with the first storage nodeand an input terminal connected with the second storage node, a firstaccess transistor that is connected between the first storage node and afirst treat line, and a second access transistor that is connectedbetween the second storage node and a second treat line. The firstinverter includes a first P-MOS transistor of a first type that isconnected between a node receiving a drain voltage and a first path nodeand operates based on an input voltage input to the input terminal, afirst N-MOS transistor of a second type that is connected between thefirst path node and the output terminal outputting an output voltage andoperates based on the drain voltage, a second P-MOS transistor of thesecond type that is connected between the output terminal and a secondpath node and operates based on a ground voltage, a second N-MOStransistor of the first type that is connected between the second pathnode and a node receiving the ground voltage and operates based on theinput voltage, a third P-MOS transistor of the second type that isconnected between the first path node and the second path node andoperates based on the input voltage, and a third N-MOS transistor of thesecond type that is connected between the first path node and the secondpath node and operates based on the input voltage. A first thresholdvoltage of each of the first P-MOS transistor, the second N-MOStransistor corresponding to the first type is lower than a secondthreshold voltage of each of the first N-MOS transistor, the secondP-MOS transistor, the third P-MOS transistor, and the third N-MOStransistor corresponding to the second type.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features of the present disclosure willbecome apparent by describing in detail embodiments thereof withreference to the accompanying drawings.

FIG. 1 is a diagram illustrating a structure of a ternary static randomaccess memory (SRAM) cell according to an embodiment.

FIG. 2 is a diagram illustrating a voltage-transfer characteristic graphfor a standard ternary inverter.

FIG. 3 is a diagram illustrating transistors included in a standardternary inverter according to an embodiment.

FIG. 4 is a diagram illustrating a structure of a standard ternaryinverter according to a comparative embodiment.

FIG. 5 is a diagram illustrating a structure of a standard ternaryinverter according to an embodiment.

FIGS. 6A to 6C are diagrams for describing an operation mechanism of astandard ternary inverter according to an embodiment.

FIGS. 7A and 7B are diagrams for describing the process in which aternary SRAM cell according to an embodiment performs a write operation.

FIGS. 8A and 8B are diagrams for describing the process in which aternary SRAM cell according to an embodiment perform a read operation.

FIG. 9 illustrates a voltage transfer characteristic graph for astandard ternary inverter and a graph for an output voltage according toan input voltage.

FIG. 10A is a diagram for describing the process of calculating a marginof a ternary SRAM cell according to an embodiment.

FIG. 10B illustrates a graph for a hold margin, a read margin, and awrite margin of a ternary SRAM cell according to an embodiment.

FIGS. 11A and 11B are diagrams for describing simulation results ofverifying a read scheme and a write scheme of a ternary SRAM cellaccording to an embodiment.

DETAILED DESCRIPTION

In embodiments of the present disclosure, specific structural orfunctional descriptions may be directed only to provide examples and maybe changed and implemented in various forms. Accordingly, an actualimplementation form is not limited to specific embodiments disclosed,and the present disclosure covers all modifications, equivalents, andalternatives falling within the spirit and scope of the invention.

The terms “first” and “second” are used to describe various elements,but it should be understood that the terms are only used to distinguishone element from another element. For example, a first element may betermed a second element; similarly, the second element may be termed thefirst element.

It should be understood that when any element is referred to as being“connected” or “coupled” to any other element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent.

The singular forms are intended to include the plural forms unless thecontext clearly indicates otherwise. In the specification, it should beunderstood that the terms “comprises”, “comprising”, “includes”, and/or“including” specify that described features, numbers, steps, operations,elements, or components or a combination thereof exists, but do notpreclude the presence or addition of one or more other features,numbers, steps, operations, elements, or components or a combinationthereof.

Unless otherwise defined, all the terms (including technical andscientific terms) used herein are to be interpreted as is customary inthe art to which the invention belongs. It will be understood that termsdefined in the dictionary used in general should be interpreted as iscustomary in the relevant art and should not be interpreted in anidealized or overly formal sense unless defined explicitly in thespecification.

Below, embodiments will be described in detail with reference to theaccompanying drawings. In the description given with reference to theaccompanying drawings, the same elements are marked by the samereference signs regardless of signs of the drawings, and repeateddescriptions thereof will be omitted.

FIG. 1 is a diagram illustrating a structure of a ternary static randomaccess memory (SRAM) cell according to an embodiment.

A ternary SRAM cell 100 according to an embodiment may include a firststandard ternary inverter 111 and a second standard ternary inverter 112that are connected in parallel. According to an embodiment, the firststandard ternary inverter 111 and the second standard ternary inverter112 may be connected with opposite polarities. In other words, the firststandard ternary inverter 111 and the second standard ternary inverter112 may be connected in a back-to-back manner.

According to an embodiment, the ternary SRAM cell 100 may furtherinclude a first access transistor 121 that connects a first storage node131 between an input terminal of the first standard ternary inverter 111and an output terminal of the second standard ternary inverter 112 witha first treat line 141. Also, the ternary SRAM cell 100 may furtherinclude a second access transistor 122 that connects a second storagenode 132 between an output terminal of the first standard ternaryinverter 111 and an input terminal of the second standard ternaryinverter 112 with a second treat line 142.

According to an embodiment, the first access transistor 121 and thesecond access transistor 122 may be implemented with an n0typetransistor (e.g., an N-MOS transistor), a drain of the first accesstransistor 121 may be connected with the first storage node 131, and adrain of the second access transistor 122 may be connected with thesecond storage node 132. Also, a source of the first access transistor121 may be connected with the first treat line 141, and a source of thesecond access transistor 122 may be connected with a second treat line142.

According to an embodiment, in the ternary SRAM cell 100, a gate of thefirst access transistor 121 and a gate of the second access transistor122 may be connected with a word line (WL) 150.

In the ternary logic, a ground voltage Gnd, a half drain voltageV_(DD)/2, and a drain voltage V_(DD) may respectively correspond toimbalance ternary logical values, that is, “0”, “1”, and “2”. Theternary SRAM cell 100 according to an embodiment may use the firststandard ternary inverter 111 and the second standard ternary inverter112 connected in the back-to-back manner as a storage element. As willbe described later, the ternary SRAM cell 100 may hold a voltagecorresponding to one ternary value at the first storage node 131 and thesecond storage node 132 by a write voltage applied to the first treatline 141 and the second treat line 142.

FIG. 2 is a diagram illustrating a voltage-transfer characteristic (VTC)graph for a standard ternary inverter (STI).

The standard ternary inverter STI may refer to a logic gate that outputsa ternary logical value of “2”, “1”, or “0” when a ternary logical valueof “0”, “1”, or “2” is received. When the standard ternary inverter STIhas appropriate voltage-transfer characteristics like a graph 200illustrated in FIG. 2 , the standard ternary inverter STI may obtain amargin sufficient to activate a tolerance to a noise. Herein, the marginmay refer to the stability. Referring to the graph 200, when the groundvoltage Gnd (e.g., 0 V) indicating the ternary value of “0” is appliedto the standard ternary inverter STI, the drain voltage V_(DD) (e.g., 1V) indicating the ternary value of “2” may be output from the standardternary inverter STI. Also, when the half drain voltage V_(DD)/2 (e.g.,0.5 V) indicating the ternary value of “1” is applied to the standardternary inverter STI, the half drain voltage V_(DD)/2 indicating theternary value of “1” may be output from the standard ternary inverterSTI; when the drain voltage V_(DD) indicating the ternary value of “2”is applied to the standard ternary inverter STI, the ground voltage Gndindicating the ternary value of “0” may be output from the standardternary inverter STI. For example, the drain voltage V_(DD) may be 1 V,but the magnitude of the drain voltage V_(DD) is not limited thereto.

FIG. 3 is a diagram illustrating transistors included in a standardternary inverter according to an embodiment.

Upon designing the standard ternary inverter, a ternary switchingoperation may be implemented by using a multi-threshold CMOS technology.As the thickness of the gate oxide TOX of the transistor increases, thethreshold voltage VTH of the transistor may increase. Referring to FIG.3 , four types of transistors may be used to implement the standardternary inverter according to an embodiment. First, a transistor 311refers to a p-type transistor (hereinafter referred to as a “P-MOStransistor”) whose gate oxide has a first thickness. A transistor 312refers to an n-type transistor (hereinafter referred to as an “N-MOStransistor”) whose gate oxide has the first thickness. A transistor 321refers to a P-MOS transistor whose gate oxide has a second thickness. Atransistor 322 refers to an N-MOS transistor whose gate oxide has thesecond thickness. Herein, the second thickness may be thicker than thefirst thickness. Accordingly, the threshold voltage of the transistorwith the second thickness is higher than the threshold voltage of thetransistor with the first thickness.

According to an embodiment, the P-MOS transistor 311 including the gateoxide of the first thickness may be turned on when a voltage applied tothe gate thereof is the ground voltage Gnd or the half drain voltageV_(DD)/2. In contrast, the P-MOS transistor 321 including the gate oxideof the second thickness may be turned on only when a voltage applied tothe gate thereof is the ground voltage Gnd.

According to an embodiment, the N-MOS transistor 312 including the gateoxide of the first thickness may be turned on when a voltage applied tothe gate thereof is the drain voltage V_(DD) or the half drain voltageV_(DD)/2. In contrast, the N-MOS transistor 322 including the gate oxideof the second thickness may be turned on only when a voltage applied tothe gate thereof is the drain voltage V_(DD).

A major issue associated with the implementation of the ternary logiccircuit is the amount of static current when the output voltage is thehalf drain voltage V_(DD)/2. The reason is that a current supplied froma voltage source leads to power dissipation. When the output of thestandard ternary inverter is the drain voltage V_(DD) or the groundvoltage Gnd, the pull-up or pull-down is completed, and thus, the staticcurrent does not flow. However, when the output of the standard ternaryinverter is the drain voltage V_(DD), the static current partiallyflows. Accordingly, to reduce the power dissipation, a method ofreducing a current when the output is the half drain voltage V_(DD)/2should be included in designing the ternary logic circuit.

FIG. 4 is a diagram illustrating a structure of a standard ternaryinverter according to a comparative embodiment.

A conventional standard ternary inverter 400 according to thecomparative embodiment may include P-MOS transistors 431 and 451 eachincluding the gate oxide of the second thickness and N-MOS transistors432 and 452 each including the gate oxide of the second thickness. Inthe specification, in the following description, a transistor includingthe gate oxide of the first thickness is referred to as a “first-typetransistor”, and a transistor including the gate oxide of the secondthickness is referred to as a “second-type transistor”.

When the input voltage applied to the standard ternary inverter 400 isthe half drain voltage V_(DD)/2, theoretically, a second-type P-MOStransistor 431 and a second-type N-MOS transistor 432 connected witheach of input nodes 411 and 412 are turned off. Because a second-typeP-MOS transistor 451 and a second-type N-MOS transistor 452 effectivelyact as a high resistance, the half drain voltage V_(DD)/2 may be outputfrom an output terminal 420 depending on the voltage division.Accordingly, a small current may be supplied to the standard ternaryinverter 400 by the voltage source.

However, when a threshold voltage of the transistor including the gateoxide of the second thickness is not sufficiently high or the transistorexists in a sub-threshold region, even though the half drain voltageV_(DD)/2 is applied to the transistor, the transistor may not becompletely turned off. When the input voltage applied to the standardternary inverter is the half drain voltage V_(DD)/2 and the transistors431 and 432 each including the gate oxide of the second thickness arenot completely turned off, there may be provided two paths through whichthe output voltage is output to the output terminal 420. For example, apath 461 may refer to a path through which a strong current flows whenthe input voltage is the half drain voltage V_(DD)/2. A path 462 mayrefer to a path through which a weak current flows when the inputvoltage is the half drain voltage V_(DD)/2.

In the standard ternary inverter 400 according to the comparativeembodiment, the path 461 through which the strong current flows may passthrough the P-MOS transistor 431 that includes the gate oxide of thesecond thickness and is connected with the input node 411. As will bedescribed later, compared to the standard ternary inverter 400 accordingto the comparative embodiment, because a strong current path passesthrough more transistors than the standard ternary inverter 400, thestandard ternary inverter according to an embodiment has a moreeffective resistance, and thus, a current that is supplied from thevoltage source decreases. As such, the standard ternary inverteraccording to an embodiment may reduce the power dissipation.

FIG. 5 is a diagram illustrating a structure of a standard ternaryinverter 500 according to an embodiment.

Referring to FIG. 1 , the ternary SRAM cell 100 according to anembodiment may include the first standard ternary inverter 111 and thesecond standard ternary inverter 112. The ternary SRAM cell 100according to an embodiment may further include the first accesstransistor 121 and the second access transistor 122. In this case, thefirst standard ternary inverter 111 and the second standard ternaryinverter 112 may include one or more transistors each including the gateoxide of the first thickness and one or more transistors each includingthe gate oxide of the second thickness thicker than the first thickness,and each of the first access transistor and the second access transistormay be a transistor including the gate oxide of the first thickness.Also, each of the first standard ternary inverter 111 and the secondstandard ternary inverter 112 may have a structure of the standardternary inverter 500 illustrated in FIG. 5 .

The standard ternary inverter 500 according to an embodiment may includea first P-MOS transistor 531 of the first type that receives the inputvoltage through a gate, and a first N-MOS transistor 541 of the secondtype that includes a drain connected with a drain of the first P-MOStransistor 531. Also, the standard ternary inverter 500 may furtherinclude a second P-MOS transistor 532 of the second type that includes asource connected with a source of the first N-MOS transistor 541, and asecond N-MOS transistor 542 of the first type that includes a drainconnected with a drain of the second P-MOS transistor 532. The standardternary inverter 500 according to an embodiment may further include athird P-MOS transistor 551 of the second type that receives the inputvoltage through a gate and a third N-MOS transistor 552 of the secondtype that receives the input voltage through a gate, and the third P-MOStransistor 551 and the third N-MOS transistor 552 may be connected inparallel.

In the standard ternary inverter 500 according to an embodiment, thethird P-MOS transistor 551 and the third N-MOS transistor 552 may bedisposed between a first path node 571 connecting the first P-MOStransistor 531 and the first N-MOS transistor 541 and a second path node572 connecting the second P-MOS transistor 532 and the second N-MOStransistor 542.

According to an embodiment, the first path node 571 may be connectedwith a source of the third P-MOS transistor 551 and a drain of the thirdN-MOS transistor 552, and the second path node 572 may be connected witha drain of the third P-MOS transistor 551 and a source of the thirdN-MOS transistor 552.

According to an embodiment, the output voltage may be output from anoutput terminal 520 with which the source of the first N-MOS transistor541 and the source of the second P-MOS transistor 532 are connected.

According to an embodiment, the source of the third P-MOS transistor 551and the drain of the third N-MOS transistor 552 may be connected withthe first path node 571, and the drain of the third P-MOS transistor 551and the source of the third N-MOS transistor 552 may be connected withthe second path node 572.

According to an embodiment, the drain voltage V_(DD) may be supplied toa source of the first P-MOS transistor 531 and a gate of the first N-MOStransistor 541, and the ground voltage Gnd may be applied to a gate ofthe second P-MOS transistor 532 and a source of the second N-MOStransistor 542.

Herein, the first-type transistor (e.g., the first P-MOS transistor 531or the second N-MOS transistor 542) may have a first threshold voltagedue to the gate oxide of the first thickness, and the second-typetransistor (e.g., the first N-MOS transistor 541, the second P-MOStransistor 532, the third P-MOS transistor 551, or the third N-MOStransistor 552) may have a second threshold voltage due to the gateoxide of the second thickness thicker than the first thickness. Thesecond threshold voltage may be greater than the first thresholdvoltage.

When the input voltage is the half drain voltage V_(DD)/2 and the firstP-MOS transistor 531 and the second N-MOS transistor 542 each includingthe gate oxide of the second thickness are not completely turned off,there may be provided two paths through which the output voltage isoutput to the output terminal 520. A path 561 may refer to a paththrough which a weak current flows when the input voltage is the halfdrain voltage V_(DD)/2. A path 562 may refer to a path through which astrong current flows when the input voltage is the half drain voltageV_(DD)/2. In the strong current path 562 of the standard ternaryinverter 500 according to an embodiment, because the third P-MOStransistor 551 and the third N-MOS transistor 552 that are connectedwith the input nodes 511, 512, and 513 and include the gate oxide of thesecond thickness effectively act as a high resistance, when the halfdrain voltage V_(DD)/2 is applied to the standard ternary inverter 500as the input voltage, a current that is supplied by the voltage sourcemay decrease.

FIGS. 6A to 6C are diagrams for describing an operation mechanism of astandard ternary inverter 600 according to an embodiment.

The mechanism that the half drain voltage V_(DD)/2 is output as theoutput voltage when the half drain voltage V_(DD)/2 is applied to thestandard ternary inverter 600 as the input voltage will be describedwith reference to FIG. 6A.

According to an embodiment, the half drain voltage V_(DD)/2 may beapplied to input terminals 611, 612, and 613 of the standard ternaryinverter 600. In th, as described above, because the second-type P-MOStransistor (i.e., a P-MOS transistor including the gate oxide of thesecond thickness) is turned on only when a voltage applied to the gatethereof is the ground voltage Gnd and the second-type N-MOS transistor(i.e., an N-MOS transistor including the gate oxide of the firstthickness) is turned on only when a voltage applied to the gate thereofis the drain voltage VDD, a third P-MOS transistor 651 of the secondtype and a third N-MOS transistor 652 of the second type and a thirdN-MOS transistor 652 of the second type may be turned off. In this case,the standard ternary inverter 600 may output the half drain voltageV_(DD)/2 to an output terminal 620 as the output voltage along a path760 that is formed of the first P-MOS transistor 631, the first N-MOStransistor 641, the second P-MOS transistor 632, and the second N-MOStransistor 642.

According to an embodiment, in the standard ternary inverter 600, thedrain voltage V_(DD) of the voltage source may be supplied to the drainof the first P-MOS transistor 631, and the ground voltage Gnd of thevoltage source may be supplied to the drain of the second N-MOStransistor 642; in this case, the first N-MOS transistor 641 and thesecond P-MOS transistor 632 may act as the high resistance. As a result,in the standard ternary inverter 600, when the half drain voltageV_(DD)/2 is applied as the input voltage, the half drain voltageV_(DD)/2 may be output from the output terminal 620 as the outputvoltage depending on the voltage division that is made on the path 670.

The mechanism that the drain voltage V_(DD) is output as the outputvoltage when the ground voltage Gnd is applied to the standard ternaryinverter 600 as the input voltage will be described with reference toFIG. 6B.

According to an embodiment, the ground voltage Gnd may be applied to theinput terminals 611, 612, and 613 of the standard ternary inverter 600.In this case, the third N-MOS transistor 652 of the second type and thesecond N-MOS transistor of the first type may be turned off. As such,the standard ternary inverter 600 may output the drain voltage V_(DD) tothe output terminal 620 as the output voltage along a path 670 that isformed of the first P-MOS transistor 631, the third P-MOS transistor651, and the second P-MOS transistor 632.

In detail, the third N-MOS transistor 652 of the second type is turnedoff when the ground voltage Gnd is applied to the input terminal 613,and the second N-MOS transistor 642 of the first type is turned off whenthe ground voltage Gnd is applied to the input terminal 612. In thestandard ternary inverter 600, the drain voltage V_(DD) may be suppliedto the source of the first P-MOS transistor 631, and the first N-MOStransistor 641 may act as the high resistance. As a result, when theground voltage Gnd is applied as the input voltage, the standard ternaryinverter 600 may output the drain voltage V_(DD) to the output terminal620 as the output voltage through the path 670.

The mechanism that the ground voltage Gnd is output as the outputvoltage when the drain voltage DD is applied to the standard ternaryinverter 600 as the input voltage will be described with reference toFIG. 6C.

According to an embodiment, the drain voltage V_(DD) may be applied tothe input terminals 611, 612, and 613 of the standard ternary inverter600. In this case, the first P-MOS transistor 631 of the first type andthe third P-MOS transistor of the second type may be turned off. Assuch, the standard ternary inverter 600 may output the ground voltageGnd to the output terminal 620 as the output voltage along a path 690that is formed of the first N-MOS transistor 641, the third N-MOStransistor 652, and the second N-MOS transistor 642.

In detail, the first P-MOS transistor 631 of the first type is turnedoff when the drain voltage V_(DD) is applied to the input terminal 611,and the third P-MOS transistor 651 of the second type is turned off whenthe drain voltage V_(DD) is applied to the input terminal 613. In thestandard ternary inverter 600, the ground voltage Gnd may be supplied tothe source of the second N-MOS transistor 642, and the second P-MOStransistor 632 may act as the high resistance. As a result, when thedrain voltage V_(DD) is applied as the input voltage, the standardternary inverter 600 may output the ground voltage Gnd to the outputterminal 620 as the output voltage through the path 690.

FIGS. 7A and 7B are diagrams for describing the process in which aternary SRAM cell according to an embodiment performs a write operation.

A ternary SRAM cell 700 according to an embodiment may perform the writeoperation. In detail, the ternary SRAM cell 700 may hold a voltageindicating a ternary value at a first storage node 731 and a secondstorage node 732.

According to an embodiment, the ternary SRAM cell 700 may hold a voltagecorresponding to one ternary value at each of the first storage node 731and the second storage node 732 by individually applying a write voltagecorresponding to the ternary value at a first treat line 741 and asecond treat line 742.

According to an embodiment, a combination of the drain voltage V_(DD)held at the first storage node 731 and the ground voltage Gnd held atthe second storage node 732 may indicate a ternary value of “2”. Also, acombination of the ground voltage Gnd held at the first storage node 731and the drain voltage V_(DD) held at the second storage node 732 mayindicate a ternary value of “0”. In addition, a combination of the halfdrain voltage V_(DD)/2 held at the first storage node 731 and the halfdrain voltage V_(DD)/2 held at the second storage node 732 may indicatea ternary value of “1”.

FIG. 7A shows the process in which the ternary SRAM cell 700 holds avoltage indicating “2” or a voltage indicating “0” at the first storagenode 731 and the second storage node 732.

According to an embodiment, the drain voltage V_(DD) may be applied tothe first treat line 741, and the ground voltage Gnd may be applied tothe second treat line 742. The drain voltage V_(DD) may be applied to aword line 750. Because the word line 750 is connected with the gate of afirst access transistor 721 and the gate of a second access transistor722, when the drain voltage V_(DD) is applied to the word line 750, thefirst access transistor 721 and the second access transistor 722 may beturned on. Also, as the drain voltage V_(DD) applied to the first treatline 741 is transferred to the source of the first access transistor721, the first storage node 731 may hold the drain voltage V_(DD). Asthe ground voltage Gnd applied to the second treat line 742 istransferred to the source of the second access transistor 722, thesecond storage node 732 may hold the ground voltage Gnd.

Also, in the ternary SRAM cell 700, the output terminal of a firststandard ternary inverter 711 may be connected with the input terminalof a second standard ternary inverter 712, and the input terminal of thefirst standard ternary inverter 711 may be connected with the outputterminal of the second standard ternary inverter 712. According to theabove description, when the drain voltage V_(DD) is applied to the firststandard ternary inverter 711, the first standard ternary inverter 711may output the ground voltage Gnd; when the ground voltage Gnd isapplied to the second standard ternary inverter 712, the second standardternary inverter 712 may output the drain voltage V_(DD). Accordingly,through the positive feedback between the first standard ternaryinverter 711 and the second standard ternary inverter 712, the drainvoltage V_(DD) of the first storage node 731 may be effectively held,and the ground voltage Gnd of the second storage node 732 may beeffectively held. As described above, a combination of the drain voltageV_(DD) held at the first storage node 731 and the ground voltage Gndheld at the second storage node 732 may indicate a ternary value of “2”.

According to an embodiment, the ground voltage Gnd may be applied to thefirst treat line 741, and the drain voltage V_(DD) be applied to thesecond treat line 742. As the drain voltage V_(DD) is applied to theword line 750, the first access transistor 721 and the second accesstransistor 722 may be turned on. As the ground voltage Gnd applied tothe first treat line 741 is transferred to the source of the firstaccess transistor 721, the first storage node 731 may hold the groundvoltage Gnd. As the drain voltage V_(DD) applied to the second treatline 742 is transferred to the source of the second access transistor722, the second storage node 732 may hold the drain voltage V_(DD). Acombination of the ground voltage Gnd held at the first storage node 731and the drain voltage V_(DD) held at the second storage node 732 mayindicate a ternary value of “0”.

FIG. 7B shows the process in which the ternary SRAM cell 700 holds avoltage indicating “1” at the first storage node 731 and the secondstorage node 732.

According to an embodiment, the half drain voltage V_(DD)/2 may beapplied to the first treat line 741, and the half drain voltage V_(DD)/2may be applied to the second treat line 742. As the drain voltage V_(DD)is applied to the word line 750, the first access transistor 721 and thesecond access transistor 722 may be turned on. As the half drain voltageV_(DD)/2 applied to the first treat line 741 is transferred to thesource of the first access transistor 721, the first storage node 731may hold the half drain voltage V_(DD)/2; as the half drain voltageV_(DD)/2 applied to the second treat line 742 is transferred to thesource of the second access transistor 722, the second storage node 732may hold the half drain voltage V_(DD)/2. A combination of the halfdrain voltage V_(DD)/2 held at the first storage node 731 and the halfdrain voltage V_(DD)/2 held at the second storage node 732 may indicatea ternary value of “1”.

FIGS. 8A and 8B are diagrams for describing the process in which aternary SRAM cell according to an embodiment may a read operation.

Referring to FIG. 8A, a ternary SRAM cell 800 may hold a voltageindicating one ternary value at a first storage node 831 and a secondstorage node 832, respectively. For the read operation of the ternarySRAM cell 800, the half drain voltage V_(DD)/2 may be applied to a firsttreat line 841 and a second treat line 842. In other words, the firsttreat line 841 and the second treat line 842 may be pre-charged with thehalf drain voltage V_(DD)/2. As the half drain voltage V_(DD)/2 isapplied to a word line 850 instead of the drain voltage V_(DD), thechange of the voltages held at the first storage node 831 and the secondstorage node 832 may be prevented.

According to an embodiment, when the read voltage is individuallyapplied to the first treat line 841 and the second treat line 842 andthe ground voltage Gnd is held at at least one of the first storage node831 and the second storage node 832, the ternary SRAM cell 800 maydischarge a treat line corresponding to a node, at which thecorresponding ground voltage Gnd is held, to the ground voltage Gnd.

In detail, referring to FIG. 8B, for the turn-on of a first accesstransistor 821 and a second access transistor 822, a gate thresholdvoltage VGS should be greater than a threshold voltage Vth. For example,when the ground voltage Gnd is held at the first storage node 831, thefirst access transistor 821 is turned on; when the half drain voltageV_(DD)/2 or the drain voltage V_(DD) is held at the first storage node831, the first access transistor 821 is turned off. Likewise, when theground voltage Gnd is held at the second storage node 832, the secondaccess transistor 822 is turned on; when the half drain voltage V_(DD)/2or the drain voltage V_(DD) is held at the second storage node 832, thesecond access transistor 822 is turned off.

According to an embodiment, when the ground voltage Gnd is held at thefirst storage node 831, the first access transistor 821 is turned on,and a current flows from the first treat line 841 to the first storagenode 831 through the first access transistor 821. The first treat line841 is discharged to the ground voltage Gnd by the ground voltage Gndheld at the first storage node 831. When the half drain voltage V_(DD)/2or the drain voltage V_(DD) is held at the first storage node 831, thefirst access transistor 821 is turned off, and thus, the first treatline 841 is not discharged.

According to an embodiment, when the ground voltage Gnd is held at thesecond storage node 832, the second first access transistor 822 isturned on, and a current flows from the second treat line 842 to thesecond storage node 832 through the second access transistor 822. Thesecond treat line 842 is discharged to the ground voltage Gnd by theground voltage Gnd held at the second storage node 832. When the halfdrain voltage V_(DD)/2 or the drain voltage V_(DD) is held at the secondstorage node 832, the second access transistor 822 is turned off, andthus, the second treat line 842 is not discharged.

To sum up, the first treat line 841 may be discharged only when theground voltage Gnd is held at the first storage node 831, and the secondtreat line 842 may be discharged only when the ground voltage Gnd isheld at the second storage node 832.

The ternary SRAM cell 800 according to an embodiment may store datacorresponding to a ternary value of “2” by holding the drain voltageV_(DD) and the ground voltage Gnd at the first storage node 831 and thesecond storage node 832, respectively. As such, the second treat line842 may be discharged to the ground voltage Gnd, and data of “2” may beread depending on the half drain voltage V_(DD)/2 output from the firsttreat line 841 and the ground voltage Gnd output from the second treatline 842.

The ternary SRAM cell 800 according to an embodiment may store datacorresponding to a ternary value of “0” by holding the ground voltageVDD and the drain voltage VDD at the first storage node 831 and thesecond storage node 832, respectively. As such, the first treat line 841may be discharged to the ground voltage Gnd, and data of “1” may be readdepending on the ground voltage Gnd output from the first treat line 841and the half drain voltage V_(DD)/2 output from the second treat line842.

The ternary SRAM cell 800 according to an embodiment may store datacorresponding to a ternary value of “1” by holding the half drainvoltage V_(DD)/2 and the half drain voltage V_(DD)/2 at the firststorage node 831 and the second storage node 832, respectively. As such,the first treat line 841 and the second treat line 842 may not bedischarged, and data of “1” may be read depending on the half drainvoltage V_(DD)/2 output from the first treat line 841 and the half drainvoltage V_(DD)/2 output from the second treat line 842.

FIG. 9 illustrates a voltage transfer characteristic (VTC) graph for astandard ternary inverter and a graph for an output voltage according toan input voltage.

A graph 910 indicates a voltage transfer characteristic of a standardternary inverter. Referring to FIG. 9 , a curve of the voltage transfercharacteristic of a standard ternary inverter 901 according to acomparative embodiment and a curve of the voltage transfercharacteristic of a standard ternary inverter 902 according to acomparative embodiment are very similar.

A graph 920 indicates an output current according to an input voltage ofa standard ternary inverter. Referring to the graph 920, the standardternary inverter 902 according to an embodiment may output, for example,a current of 1.46 μA when the input voltage is the half drain voltageV_(DD)/2 (e.g., 0.5 V), and the standard ternary inverter 901 accordingto the comparative embodiment may output a current of 1.89 μA when theinput voltage is the half drain voltage V_(DD)/2. An output current ofthe standard ternary inverter 902 according to an embodiment may besmaller than that of the standard ternary inverter 901 according to thecomparative embodiment as much as 22.75%, and thus, the powerdissipation of the standard ternary inverter 902 may be drasticallyreduced.

FIG. 10A is a diagram for describing the process of calculating a marginof a ternary SRAM cell according to an embodiment.

A ternary SRAM cell according to an embodiment may guarantee thestability of the hold operation, the read operation, and the writeoperation. First, three SNMs may be measured with respect to the ternarySRAM cell. The three SNMs indicate a hold margin HM, a read margin RM,and a write margin WM. Referring to FIG. 10A, standard ternary inverters1011 and 1021 may be used to calculate the hold margin HM, the readmargin RM, and the write margin WM of the ternary SRAM cell according toan embodiment. A voltage level that is required for each node may beidentified. After the voltage level of each node of the ternary SRAMcell is set, the hold margin HM, the read margin RM, and the writemargin WM may be measured by using a DC analysis and butterfly curvemanner.

FIG. 10B illustrates a graph for a hold margin, a read margin, and awrite margin of a ternary SRAM cell according to an embodiment.

The stability of voltage holding may be identified in the ternary SRAMcell according to an embodiment. In other words, whether a voltageindicating one ternary value is capable of being effectively held atstorage nodes of the ternary SRAM cell may be determined through thehold margin. A graph 1031 of FIG. 10B is a graph for calculating a holdmargin of a ternary SRAM cell according to an embodiment. In a circuit1010 of FIG. 10A, the ground voltage Gnd may be applied to a gate of atransistor for the purpose of measuring the hold margin of the ternarySRAM cell. In this case, the output voltage of the output terminal ofthe standard ternary inverter 1011 may be identified by applying avoltage, which sweeps from the ground voltage Gnd to the drain voltageV_(DD), to the input terminal of the standard ternary inverter 1011. Inthis case, a graph 1031 may include a curve in which an X valueindicates the input voltage applied to the input terminal of thetransistor in the circuit 1010 and a Y value indicates the outputvoltage output from the output terminal of the transistor in the circuit1010. Also, in the circuit 1020, the ground voltage Gnd may be appliedto a gate of a transistor. In this case, the output voltage of theoutput terminal of the standard ternary inverter 1021 may be identifiedby applying a voltage, which sweeps from the ground voltage Gnd to thedrain voltage V_(DD), to the input terminal of the standard ternaryinverter 1021. In this case, the graph 1031 may further include a curvein which a Y value indicates the input voltage applied to the inputterminal of the transistor in the circuit 1020 and an X value indicatesthe output voltage output from the output terminal of the transistor inthe circuit 1020. For example, through the graph 1031, the hold marginmay be calculated to be 131 mV corresponding to a length of one side ofa quadrangle 1041.

As in the above description, there may be calculated the read margin andthe write margin of the ternary SRAM cell according to an embodiment. Agraph 1032 is a graph for calculating the read margin of the ternarySRAM cell according to an embodiment. For example, through the graph1032, the read margin may be calculated to be 131 mV. Graphs 1033 and1034 are graphs for calculating the hold margin of the ternary SRAM cellaccording to an embodiment. In detail, the graph 1033 is a graph forcalculating the write margin when the ternary SRAM cell according to anembodiment stores data corresponding to a ternary value of “1”. Thegraph 1034 is a graph for the write margin when the ternary SRAM cellaccording to an embodiment stores data corresponding to ternary valuesof “0” and “2”. For example, through the graph 1033, the write marginmay be calculated to be 328 mV; through the graph 1034, the write marginmay be calculated to be 225 mV. The hold operation and the readoperation may have the same noise margin. In the cased of the ternarySRAM cell, because the hold margin and the read margin are the smallestamong the tree SNMs, the hold operation and the read operation have theweakest tolerance to the noise.

FIGS. 11A and 11B are diagrams for describing simulation results ofverifying a read scheme and a write scheme of a ternary SRAM cellaccording to an embodiment.

FIG. 11A shows a circuit 1100 for performing a read operation and awrite operation of a ternary SRAM cell 1110 according to an embodiment.FIG. 11B shows a graph indicating voltages applied or generated everynodes and lines when the read operation and the write operation of theternary SRAM cell 1110 are performed.

A voltage may be held at a first storage node (Q) 1111 in the order ofthe drain voltage V_(DD), the half drain voltage V_(DD)/2, and theground voltage Gnd depending on the write scheme.

For example, the process where the ternary SRAM cell 1110 according toan embodiment stores data corresponding to a ternary value of “2” willbe described. To allow the first storage node (Q) 111 to hold the drainvoltage V_(DD) and a second storage node (QB) 1112 to hold the groundvoltage Gnd, the drain voltage V_(DD) may be applied to a node (WRITE)1121 of a write driver 1120, and the drain voltage V_(DD) may be appliedto a node (DATA) 1122; in this case, the drain voltage V_(DD) may beapplied to a first treat line 1131, and the ground voltage Gnd may beapplied to a second treat line 1132. In this case, the first storagenode 1111 may hold the drain voltage V_(DD), and the second storage node1112 may hold the ground voltage Gnd. The view 1181 of FIG. 11B showsthat when the drain voltage V_(DD) (e.g., 1 V) is applied to a word line1113, the drain voltage V_(DD) (e.g., 1 V) is applied to the node(WRITE) 1121, and the drain voltage V_(DD) (e.g., 1 V) is applied to thenode (DATA) 1122, the first storage node (Q) 1111 holds the drainvoltage V_(DD), and the second storage node (QB) 1112 holds the groundvoltage Gnd.

For another example, the process where the ternary SRAM cell 1110according to an embodiment stores data corresponding to a ternary valueof “0” will be described. To allow the first storage node (Q) 111 tohold the ground voltage Gnd and the second storage node (QB) 1112 tohold the drain voltage V_(DD), the drain voltage V_(DD) may be appliedto the node (WRITE) 1121 of the write driver 1120, and the groundvoltage Gnd may be applied to the node (DATA) 1122; in this case, theground voltage Gnd may be applied to the first treat line 1131, and thedrain voltage V_(DD) may be applied to the second treat line 1132. Inthis case, the first storage node 1111 may hold the ground voltage Gnd,and the second storage node 1112 may hold the drain voltage DD. The view1182 of FIG. 11B shows that when the drain voltage V_(DD) (e.g., 1 V) isapplied to the word line 1113, the drain voltage V_(DD) (e.g., 1 V) isapplied to the node (WRITE) 1121, and the ground voltage Gnd is appliedto the node (DATA) 1122, the first storage node (Q) 1111 holds theground voltage Gnd, and the second storage node (QB) 1112 holds thedrain voltage V_(DD).

For another example, the process where the ternary SRAM cell 1110according to an embodiment stores data corresponding to a ternary valueof “1” will be described. As the drain voltage V_(DD) is applied to anode (PRE) 1141, the half drain voltage V_(DD)/2 may be applied to thefirst treat line 1131 and the second treat at the 1132. In this case,the first storage node 1111 may hold the half drain voltage V_(DD)/2,and the second storage node 1112 may also hold the half drain voltageV_(DD)/2. The view 1183 of FIG. 11B shows that when the drain voltageV_(DD) (e.g., 1 V) is applied to the word line 1113 and the drainvoltage V_(DD) is applied to the node (PRE) 1141, the first storage node(Q) 1111 holds the half drain voltage V_(DD)/2, and the second storagenode (QB) 1112 holds the half drain voltage V_(DD)/2.

In this case, the first storage node 1111 may hold the ground voltageGnd, and the second storage node 1112 may hold the drain voltage DD.

In addition, to implement the read operation, the drain voltage V_(DD)may be applied to the node (PRE) 1141, and thus, a pre-charging circuit1140 may be turned on. As described above, the first treat line 1131 andthe second treat line 1132 may be pre-charged with the half drainvoltage V_(DD)/2. Next, the half drain voltage V_(DD)/2 may be appliedto the word line 1113; in this case, the first treat line 1131 may bedischarged when the ground voltage Gnd is held at the first storage node1111, and the second treat line 1132 may be discharged when the groundvoltage Gnd is held at the second storage node 1112. A data value storedin the ternary SRAM cell 1110 may be determined by sensing a voltagedifference of the first treat line 1131 and the second treat line 1132.The view 1184 of FIG. 11B shows that when the half drain voltageV_(DD)/2 (e.g., 0.5 V) is applied to the word line 1113 and the drainvoltage V_(DD) (e.g., 1 V) is applied to the node (PRE) 1141, the firsttreat line 1131 is discharged to the ground voltage Gnd by the groundvoltage Gnd held at the first storage node (Q) 1111.

According to an embodiment of the present disclosure, as an inverter isimplemented with transistors having different threshold voltages, powerdissipation of a memory cell including the inverter may be reduced, andthe reliability of an operation of storing multiple values.

While the present disclosure has been described with reference toembodiments thereof, it will be apparent to those of ordinary skill inthe art that various changes and modifications may be made theretowithout departing from the spirit and scope of the present disclosure asset forth in the following claims.

What is claimed is:
 1. An inverter comprising: a first P-MOS transistorconnected between a node receiving a drain voltage and a first pathnode, and configured to operate based on an input voltage; a first N-MOStransistor connected between the first path node and an output terminaloutputting an output voltage, and configured to operate based on thedrain voltage; a second P-MOS transistor connected between the outputterminal and a second path node, and configured to operate based on aground voltage; a second N-MOS transistor connected between the secondpath node and a node receiving the ground voltage, and configured tooperate based on the input voltage; a third P-MOS transistor connectedbetween the first path node and the second path node, and configured tooperate based on the input voltage; and a third N-MOS transistorconnected between the first path node and the second path node, andconfigured to operate based on the input voltage, wherein the firstP-MOS transistor has a first threshold voltage, wherein each of thesecond P-MOS transistor and the third P-MOS transistor has a secondthreshold voltage higher than the first threshold voltage, wherein thesecond N-MOS transistor has a third threshold voltage, and wherein eachof the first N-MOS transistor and the third N-MOS transistor has afourth threshold voltage higher than the third threshold voltage.
 2. Theinverter of claim 1, wherein the first threshold voltage is identical tothe third threshold voltage, and wherein the second threshold voltage isidentical to the fourth threshold voltage.
 3. The inverter of claim 1,wherein the third P-MOS transistor includes a source node connected withthe first path node and a drain node connected with the second pathnode, and wherein the third N-MOS transistor includes a drain nodeconnected with the first path node and a source node connected with thesecond path node.
 4. The inverter of claim 1, wherein the first P-MOStransistor has the first threshold voltage by a gate oxide of a firstthickness, and wherein each of the second P-MOS transistor and the thirdP-MOS transistor has the second threshold voltage by a gate oxide of asecond thickness thicker than the first thickness.
 5. The inverter ofclaim 4, wherein the second N-MOS transistor has the third thresholdvoltage by a gate oxide of a third thickness, and wherein each of thefirst N-MOS transistor and the third N-MOS transistor has the fourththreshold voltage by a gate oxide of a fourth thickness thicker than thethird thickness.
 6. The inverter of claim 5, wherein the first thicknessis identical to the third thickness, and wherein the second thickness isidentical to the fourth thickness.
 7. The inverter of claim 1, wherein,when a half drain voltage is applied as the input voltage, the thirdP-MOS transistor and the third N-MOS transistor are turned off, thefirst P-MOS transistor, the first N-MOS transistor, the second P-MOStransistor, and the second N-MOS transistor are turned on, and theoutput voltage is the half drain voltage.
 8. The inverter of claim 1,wherein, when the ground voltage is applied as the input voltage, thesecond N-MOS transistor and the third N-MOS transistor are turned off,the first P-MOS transistor, the second P-MOS transistor, and the thirdP-MOS transistor are turned on, and the output voltage is the drainvoltage.
 9. The inverter of claim 1, wherein, when the drain voltage isapplied as the input voltage, the first P-MOS transistor and the thirdP-MOS transistor are turned off, the first N-MOS transistor, the secondN-MOS transistor, and the third N-MOS transistor are turned on, and theoutput voltage is the ground voltage.
 10. A memory cell comprising: afirst inverter including an input terminal connected with a firststorage node and an output terminal connected with a second storagenode; a second inverter including an output terminal connected with thefirst storage node and an input terminal connected with the secondstorage node; a first access transistor connected between the firststorage node and a first treat line; and a second access transistorconnected between the second storage node and a second treat line,wherein the first inverter includes: a first P-MOS transistor of a firsttype connected between a node receiving a drain voltage and a first pathnode, and configured to operate based on an input voltage input to theinput terminal; a first N-MOS transistor of a second type connectedbetween the first path node and the output terminal outputting an outputvoltage, and configured to operate based on the drain voltage; a secondP-MOS transistor of the second type connected between the outputterminal and a second path node, and configured to operate based on aground voltage; a second N-MOS transistor of the first type connectedbetween the second path node and a node receiving the ground voltage,and configured to operate based on the input voltage; a third P-MOStransistor of the second type connected between the first path node andthe second path node, and configured to operate based on the inputvoltage; and a third N-MOS transistor of the second type connectedbetween the first path node and the second path node, and configured tooperate based on the input voltage, wherein a first threshold voltage ofeach of the first P-MOS transistor, the second N-MOS transistorcorresponding to the first type is lower than a second threshold voltageof each of the first N-MOS transistor, the second P-MOS transistor, thethird P-MOS transistor, and the third N-MOS transistor corresponding tothe second type.
 11. The memory cell of claim 10, wherein each of thefirst P-MOS transistor, the second N-MOS transistor corresponding to thefirst type has the first threshold voltage by a gate oxide of a firstthickness, and wherein each of the first N-MOS transistor, the secondP-MOS transistor, the third P-MOS transistor, and the third N-MOStransistor corresponding to the second type has the second thresholdvoltage by a gate oxide of a second thickness thicker than the firstthickness.
 12. The memory cell of claim 11, wherein, when a half drainvoltage is applied as the input voltage, the third P-MOS transistor andthe third N-MOS transistor are turned off, the first P-MOS transistor,the first N-MOS transistor, the second P-MOS transistor, and the secondN-MOS transistor are turned on, and the output voltage is the half drainvoltage.
 13. The memory cell of claim 11, wherein, when the groundvoltage is applied as the input voltage, the second N-MOS transistor andthe third N-MOS transistor are turned off, the first P-MOS transistor,the second P-MOS transistor, and the third P-MOS transistor are turnedon, and the output voltage is the drain voltage.
 14. The memory cell ofclaim 11, wherein, when the drain voltage is applied as the inputvoltage, the first P-MOS transistor and the third P-MOS transistor areturned off, the first N-MOS transistor, the second N-MOS transistor, andthe third N-MOS transistor are turned on, and the output voltage is theground voltage.